Tutorial Listing, Monday, November 2, 2015
|Session 1||Session 2|
|8:00 AM - 12:00 PM||Automatic Testing from A to Z||Diagnostics and Design for Built-In Test|
|1:00 PM - 5:00 PM||ATE and TPS Management||VXI, PXI, IVI, LXI and AXIe Standards Improve ATE Systems Design|
IEEE AUTOTESTCON tutorial attendees receive Continuing Education Unit (CEU) credits. The tutorial program has been approved to award CEUs to eligible participants. Qualifying attendees will receive 0.4 CEUs for each successfully completed tutorial and 0.8 CEUs for participating in a full day. CEUs can be converted to Professional Development Hours (PDH) required by many states to maintain a professional engineering license. A full day of successful attendance will provide 8 PDH units. CEUs are awarded through the International Association for Continuing Education and Training. The Institute of Electrical and Electronic Engineers, Inc. (IEEE) is an Authorized CEU Sponsor Member of the International Association of Continuing Education and Training.
8:00 AM - 12:00 PM (Monday – November 2nd)
Instructor: Craig Stoldt, BAE Systems
This Tutorial provides a complete overview of the world of ATE from a practical engineering and management viewpoint. Beginning by examining the ATE interfaces and their limitations, it offers managers and project engineers a quick and purposeful insight into the probable sources and causes of potential technical and management problems. Working from the interfaces, the Tutorial explores analog and digital test methods, examines the impact of new instrument technologies and covers the basics of switching systems and pin electronics.
The Tutorial will explore the elements of ATE SW, examining the role of each and the scaled limitations that they impose at the s level. ATE languages will also be discussed and the different language types analyzed to determine their effect on ATE and TPS performance
Software now makes up over 50% of almost all military systems so no discussion of Automated Testing would be complete without exploring the need to consider SW testing as an integral part of the ATS environment. The Tutorial will discuss the impact of the growth in SW, look at some catastrophic example of what happens when we inadequately test software and discuss test requirements and methods.
The Tutorial will conclude with a discussion of recent changes in DoD acquisition strategies and their potential impact on the future of ATE. Interoperability, net-centric operations, nanotechnology and smart sensors are high on OSD’s wish-list for new systems and will become an inherent part of the test and maintenance process. Explore DoD’s vision of the next generation of systems, where Test & Evaluation, Condition Based Maintenance, Training and Battle Damage Assessment become by-products of a distributed hierarchical, real-time information network. The future may be closer than you think!
8:00 AM – 12:00 PM (Monday – November 2nd)
Instructors: Dr. John W. Sheppard, Montana State University
Louis Y. Ungar, A.T.E. Solutions, Inc.
This tutorial combines materials from two previous tutorials taught at IEEE AUTOTESTCON for many years. It provides attendees with a comprehensive overview of the challenges for Diagnostics and for implementation solutions through built-in [self] test (BI[S]T), often called embedded test.
The diagnostics section of this Tutorial provides an overview of traditional and more recent approaches to system-level diagnosis and prognosis. The emphasis is placed on different system modeling approaches and the algorithms that can be applied using resulting models. The Tutorial will review the basic issues and challenges in system diagnosis and prognosis. Fundamental terms and concepts of fault diagnosis will be presented with focus being given to historical approaches and the needs from the perspectives of the Department of Defense. Recent initiatives such as DoD ATS Framework, ARGCS, and ATML will also be introduced.
Central to this part of the Tutorial will be a continuing discussion of how one handles uncertainty in the diagnostic and prognostic process. It will include recent developments in applying Bayesian techniques and extensions such as hidden Markov models and dynamic Bayesian networks to fault diagnosis and prognosis. Prognosis will be related to the diagnosis problem in the context of “predictive” classification, and Bayesian extensions, will be discussed.
Health Management Information Integration will also be addressed and will focus on using formal models, called ontologies, to define the semantics of the required information and then focus on processes for maturing diagnostic applications as maintenance information is collected. Throughout the discussion, the Tutorial will draw upon experiences of the instructors and participants to highlight issues related to diagnostic development within defense and commercial environments.
With increased circuit and system complexity in recent years almost every test approach has had to settle for lower fault coverage, more difficulty in diagnoses and all at greater costs. The notable exceptions are BIT, BIST and embedded test, techniques that are combined in our discussions. BIST is a phenomenon that capitalizes on greater circuit complexity (intelligence), better fault isolation from a hierarchical allocation of tests, and does not rely on costly external automatic test equipment (ATE) and test program sets (TPS). Can ATE be eliminated from servicing and repairing units under test (UUTs) in the field? Testability features introduced through the JTAG/IEEE-1149.1 boundary scan enable in situ non-interfering observability of signals even as the system is performing its normal mission (i.e. while the airplane is flying). With internal BIST in many memories and processors, one can assess system level health and achieve diagnostic resolutions discussed in the first part of this tutorial. The recently introduced IEEE-1687 provides hierarchical test capabilities allowing system level access not only to board signals but to registers within the ICs themselves. Those registers can store health status of the chip, thus enabling not only IC test at the system level but also fault isolation to the IC itself. If the faulty IC is a large part of the board or subsystem cost, we can decide to forego repairing the replaced item altogether.
While the technology is arguably available to eliminate ATE and TPS while achieving the same or better levels of fault detection and fault isolation for increasingly more complex circuits, it does not come without costs or considerations. Embedded test or BIT requires purposeful design activities at the earliest possible development stages. Design for testability (DFT) has to be considered at the conceptual design stage, even before specifications are finalized. The test and design engineers must work together to achieve a supportable system, which may include commercial off the shelf (COTS) as well as custom designs. A new management paradigm needs to be implemented in which test is part of the design. The tutorial will discuss the management aspects of such a paradigm, which incidentally have been outlined years ago by MIL-STD now MIL-HDBK-2165.
This Tutorial is aimed at professionals in all areas of support, including reliability, maintainability and logistics, as well as engineers and managers from design, test, and quality assurance.
1:00 PM – 5:00 PM (Monday – November 2nd)
Moderator: Craig Stoldt, BAE Systems
- Tony Conard, US Navy
- Craig Stoldt, BAE Systems
- Steven D. Laise, US Army
- Mark J. Cain, US Air Force
This four-part Tutorial is designed to cover the controversial and challenging issues of managing ATE and TPS development. This session is a must for all industry and government ATE/TPS managers. As with the morning ATE session, it focuses on real world situations and explores areas of frequent problems.
Part I - TPS Acquisition, Tony Conard, US Navy
This part explores processes and challenges facing the government Acquisition Manager, providing in-depth insight on acquisition topics and processes from Acquisition Planning, including the implementation of Systems Engineering, RFP development, Acquisition oversight, testing and fielding. The NAVAIR Generic OTPS RFP (NGOR) is a crucial component of the NAVAIR acquisition process that provides a standard tailorable RFP for the procurement of Operational Test Program Sets (OTPSs). This session covers requirements and issues faced by the military in acquiring TPSs from a Navy perspective, however, the acquisition topics and challenges covered focuses on areas that are common to DOD OTPS procurements and management.
Part II - TPS Development Management, Craig Stoldt, BAE Systems
This session will discuss the various challenges that a TPS development program must overcome to be successful. We will define the measureable objectives to be obtained in the technical, schedule and quality arenas. These objectives can only be met through the management of resource availability. Each discipline involved requires timely access to documentation, physical assets and various support personnel. We will outline the flow of this development process from contract inception through the phases of TRD design, review cycles, ATE acquisition, ITA fabrication, software coding, personnel scheduling and acceptance. As each contract or internal project is different, this modular approach should help the user assess those areas that are pertinent to their needs and apply the “lessons learned” presented to their own needs to facilitate a successful TPS development project.
By planning a program as if it were its own design and development product project, an organization can minimize the loosely controlled concept of test development being just a tail end of the “real” development effort of the prime hardware. A TPS requires all of the same disciplines that are managed in the development of an avionics box, and often brings some additional challenges that are imposed based on the availability of key assets and documentation. This session will highlight the phases of development and the points in the process that can be assessed for review to prevent false starts and major cost and schedule impacts.
Part III -Managing in a Dynamic Environment, Steven D. Laise, US Army
This part discusses the various reasons a TPS Engineer, Quality Engineer and Management will encounter changes with the development platform and environment during TPS Development. It will focus on the various management tools, programmatic actions and options that are available to the TPS & ATE developers and managers. Each of the ATE change categories from relatively simple to a system in Engineering Development will be reviewed and discussed along with evaluating the corresponding impact to TPS management and product acceptance of both the ATE and the TPS baseline.
It will provide a candid discussion of the magnitude of the challenges from each type of change category, along with the options of how to best overcome them with minimal impact to the project. Real world examples experienced by the US Army will be shared, highlighting the final results. Options and examples of TPS product acceptance and lessons learned will also be shared.
Part IV - Depot TPS/ATE Management, Mark J. Cain, US Air Force
This session covers the tasks and challenges faced by the USAF in managing its Depot ATE and associated TPSs. It will lead attendees through the roles and responsibilities of a variety of stakeholders involved in the management of these two interdependent commodities. Included will be the distinct paths available to the Depots and their customers for replacement or acquisition of Depot ATE and TPSs. One avenue to be explored will be that of the Capital Improvement Program (CIP) process. The CIP is frequently used in USAF Depots when replacing obsolete ATE and re-hosting the associated TPSs. We will also explore how Depot ATS capability may be acquired using the Depot Maintenance Activation Planning (DMAP) process used when transitioning or starting up a Depot repair workload from a weapon system OEM or Prime. From weapon system, supply chain, Depot, and product group managers, this session will seek to provide information on how Depot ATE and TPSs are managed throughout their lifecycle.
In addition to the four major parts covered, the tutorial instructors represent the four major players in TPS and ATE, namely, the US Navy, the US Army, the US Air Force and the civilian contractor. Questions peculiar to any of these entities can be addressed by someone close to the issue.
1:00 PM - 5:00 PM (Monday – November 2nd)
Instructor: Bob Helsel, currently manages the following T&M consortia: VXIbus Consortium, PXI Systems Alliance, IVI Foundation, LXI Consortium, and AXIe Consortium.
The VXIbus architecture was introduced 28 years ago, and is currently a well-established architecture used extensively in military, aerospace and commercial applications. However, many test engineers have no personal experience with it, or would like to brush up on its basics, as it will be around for another 10-20 years. We will cover the approval in 2004 of the VXI-1 Rev 3.0 spec, which again doubles the backplane speed to 160MB/s. And we will cover the approval of VXI 4.0 and its improvements in speed and flexibility. VXIplug&play standards are the software equivalent to the VXI hardware specifications, and are the definition to which all VXI drivers are now written. This software standard has formed the bedrock for many other software developments, such as Interchangeable Virtual Instrument (IVI) drivers.
PXI is a newer, more compact, faster hardware standard based on CompactPCI. It applies the same extensions to CPCI that VXI did to VME. This modular instrument standard rapidly gained acceptance and can be viewed as a companion standard to VXI, (or by some as a replacement). This 17-year-old hardware standard will be discussed in detail, as will its expected impact on the market. An update will be provided on Enhanced PXI specifications and their implementation, including Low Power Chassis. PXI Express and PXI MultiComputing will be explained with a review of PXI express products and their potential applications.
The Interchangeable Virtual Instrument (IVI) software standard, which has been extensively revised and expanded, will be covered with the latest information available. The IVI Foundation was founded in 1998 and incorporated in 2001. The purpose of the IVI Foundation is promoting specifications for programming test instruments that simplify interchangeability, provide better performance, and reduce the cost of program development and maintenance. IVI Instrument drivers have been available for about 12 years. New Specifications for Digital Test, Counter/Timer, and Signal Oriented test plus LXI triggering and sync will also be discussed.
The LXI Consortium is 11 years old now, and was formed to standardize the way instruments can be connected and controlled via the Internet in a Local Area Network. Extensions for discovery, triggering and synchronization, browser interface, initialization, and programming are all part of the extensions being considered in this standardization effort. We will introduce the latest release of the LXI Specification as well as the introduction of new LXI compliant products that are now available.
An emerging test and measurement standard called AXIe, AdvancedTCA eXtensions for Instrumentation, is expected to find wide acceptance within the Automatic Test Equipment community as it offers many key benefits. It is expected that a large number of COTS (commercial off-the-shelf) signal conditioning, acquisition and processing modules will become available from a range of different suppliers. AXIe uses AdvancedTCA® as its base standard, but then leverages test and measurement industry standards such as PXI, IVI, and LXI, which were designed to facilitate cooperation and plug-and-play interoperability between COTS instrument suppliers. This enables AXIe systems to easily integrate with other test and measurement equipment. AXIe's large board footprint, available power and efficient cooling to the module payload allows high density in a 19" rack space, enabling the development of high-performance instrumentation in a density unmatched by other instrumentation form factors. Channel synchronization between modules is flexible and provided by AXIe's dual triggering structures: a parallel trigger bus, and radially-distributed, time-matched point-to-point trigger lines. Inter-module communication is also provided with a local bus between adjacent modules allowing data transfer rates up to 10 Gbits/s in each direction, for example between front-end digitizer modules and DSP banks. AXIe is a next-generation, open standard that extends AdvancedTCA® for general purpose and semiconductor test. First specifications were released in June 2010, and a 12-bit, 8 channel AXIe digitizer was elected as the 2013 TM Best in Test winner of the category signal analyzer.
This comprehensive update on the development of commercial standards for the ATE community should not be missed by anyone concerned with current and future ATE systems design and integration.